Over the decades, as the integrated circuit industry kept pace with Moore’s Law – the prediction that the number of transistors in an IC would double approximately every one-and-a-half to two years – smaller and more efficient transistor designs produced faster, more powerful, more energy-efficient microchips.
This constant advancement has fueled advances in everything from cloud computing to smartphones, virtual reality to robotics, and additive fabrication to the Internet of Things (IoT).
But as the cost and complexity of each new process node has continued rising, advances have slowed noticeably, despite the fact that there are applications such as AI and machine learning, big data analysis and data center servers that require the latest and most powerful CMOS solutions.
Why? It has become so much more difficult to use MOSFET scaling techniques to achieve continued miniaturization that perpetuating Moore’s Law may finally pose manufacturing and fab-cost challenges that cannot be met.
From Planar MOSFET to FinFET
Since its introduction in 1959, the field-effect transistor (FET) has been mostly built in the plane of the silicon. In 2012, at 20nm, the industry made the first transition from “planar” MOSFETs to fin field-effect transistor (FinFET) architectures to maintain the Moore’s Law scaling path.
In a FinFET, the channel between source and drain terminals is in the form of a fin. As compared to planar transistors, the fin – contacted on three sides by the gate – provided better control of the channel formed within the fin. As a result, FinFETs helped significantly with current leakage. Since then, fin height has been increased to obtain a higher device drive current at the same footprint. Today's designs place the gate stack directly above the channel area.
One problem is that as these structures become smaller, it becomes more difficult to block the charge leak across the transistor. With FinFETs, the gate surrounds the rectangular silicon fin on three sides, leaving the bottom side connected to the body of the silicon. This allows some leakage current to flow when the transistor is off. The resulting leakage leads to hotter, less power-efficient microchips.
Stacked Nanosheets Take the Stage
As scaling is pushed beyond 5nm, the FinFET roadmap seems to be running out of steam.
The initial technology beyond the FinFET will be the stacked nanosheet transistor. This is broadly part of a concept that may also be described as gate all around or GAA transistors, which address several challenges around FinFETs for the 3nm node and beyond, promising performance boosts of more than 25 percent and power consumption reductions of more than 50 percent.
Instead of using a stack of nanowires to bridge the source and drain, a stack of thin sheets of silicon is utilized. Unlike FinFET technology, in nanosheet technology the gate surrounds the channel region in its entirety, providing even better control of current leakage. This stacked structure supports far more advanced semiconductor fabrication processes, including a channel region that is tilted upward to create a wider path for current.
Rather than the transistor consisting of a vertical fin of silicon, the nanosheet’s channel region consists of multiple, horizontal, nanometer-thin sheets stacked atop one another. Nanosheet FETs incorporate several components, including a channel, which allows electrons to flow through the transistor.
Vertically stacked nanosheet transistors could be envisioned as placing a FinFET on its side, then dividing it into separate horizontal sheets which make up the channels. A gate fully wraps around the channel to provide better channel control compared to a multi-gate FinFET with limited additional process complexity.
Advantages of Nanosheet Devices
One of the key advantages of a nanosheet device is its short channel control, which is critical to threshold voltage variation (Vth). Smaller Vth variation is essential to achieving good performance. Nanosheets offer excellent electrostatics and short channel control, and can be fabricated with minimal deviation from FinFET.
On the other hand, multiple Vth here comes with more restrictive requirements on dimensions (because of limited-sheet-to-sheet space). Still, researchers have demonstrated nanosheet transistors with more than 50 percent lower Vth variations.
Key advantages of these new transistors over FinFETs include design flexibility, especially in adjusting the effective width, or Weff, of the transistor channel. More width means you can drive more current and switch a transistor on and off more quickly. These sheets can be made wide to boost current, or narrow to limit power consumption. For example, a nanosheet with a wider sheet provides more drive current and performance. A narrow nanosheet has less drive current, but takes up a smaller area. The narrow nanosheet also requires a more complicated, costly manufacturing process.
In this way, stacked Nanosheets offer versatile design options for performance and power management thanks to the benefits of its large Weff that makes it possible to match aggressively-scaled FinFETs, even achieving a 30 percent increase in Weff when wide nanosheets are used. The idea is to increase the width of the channel in a smaller transistor, while maintaining tight control over leakage current – thus providing a better performing, lower-power device.
The logic circuits behind digital devices today rely on pairing two types of transistors—NMOS and PMOS. The same voltage signal that turns one of them on turns the other off. Electricity flows only when a bit changes, cutting down on power consumption. Shrinking circuits further will require stacking NMOS and PMOS pairs so that one is atop the other. Research departments investigating stacked nanosheets designs, such as Intel’s, have a two-nanosheet NMOS atop a three-nanosheet PMOS. In nanosheet FETs, each tiny sheet makes up a channel. The first nanosheet FETs will incorporate silicon-based channel materials for both p and n devices.
All of these advantages make stacked nanosheet devices an attractive solution as a replacement of FinFETs.
Which Process is Best for Your Application?
Keep in mind, though, that not all chips currently being produced require FinFETs. Analog, RF and other components are built around more mature processes and are still in high demand. FinFETs will still be viable for chips from 16nm to 5nm, while planar transistors will remain the mainstream technology at 22nm and above.
Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s FinFET transistors to GAA FETs at the 3nm and 2nm nodes, starting either next year or in 2023. GAA FETs hold the promise of better performance, lower power and lower leakage.
Samsung plans to introduce the world’s first nanosheets at 3nm in the 2022-2023 time frame. TSMC is developing 2nm GAA for initial launch in 2024 or 2025.The technology will require entirely new fabs. With the cost of these new fabs in the $20 billion range, this isn't something the industry is approaching without careful consideration.
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