For almost 20 years, processors have featured vertical channel transistors known as FinFETs. One of the main characteristics of FinFETs is that they are tall relative to their width and, as a result, look like fins. As compared to planar transistors, the fin – contacted on three sides by the gate – provides better control of the channel formed within the fin. As a result, FinFETs have been able to better deal with current leakage. In addition, fin height has been increased to obtain a higher device drive current at the same footprint.
FinFET devices, however, will soon be reaching their limits for scaling. At the 3nm process node and beyond, FinFETs may no longer control the leakage current properly, so it is expected that today’s FinFET transistors will gradually give way to nanosheet transistors in high-volume manufacturing.
Nanosheets are a type of a gate-all-around (GAA) device that offer better scaling and performance per unit area. This is the logical next step from FinFETs because the processing is similar to FinFETs with a limited number of changes required. In a GAA FET, the logic gates are located around the transistor instead of between the current’s source and the drain. In horizontally stacked GAA structures, short channel control can be accomplished with minimal deviation from the FinFET. Short-channel effects occur in MOSFETs in which the channel length is comparable to the depletion layer widths of the source and drain junctions.
Complex logic designs are built up from standard cells, so in order to continue to scale logic we need to continually shrink the size of standard cells. One way to do this is to reduce cell height, which is defined as the number of metal lines (or tracks) per cell times the metal pitch.
Process limitations will, however, pose a limit to how close the nanosheet’s n and p devices can be brought together, challenging further cell height reduction. Both FinFET and nanosheet architectures feature a large n-to-p device separation distance, hindering further scalability.
Any further reduction of cell height will require a much tighter spacing between nFET and pFET devices within the cell. One solution garnering favor is called a forksheet device, a type of GAA controlled by a forked gate structure with a dielectric wall in between the p and n devices. This wall physically isolates the p-gate trench from the n-gate trench, allowing a much tighter n-to-p spacing than is possible with either FinFET or nanosheet devices.
With a forksheet design, the available space also can be used to increase the sheet width and, as such, enhance the drive current.
In July, Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, hosted its annual International Technology Forum in which it proposed a 20-year roadmap on how the industry can continue to enable higher performing semiconductor technologies. Luc Van den hoves, Imec’s president and CEO, presented a roadmap that leaned heavily on forksheet devices in which the n- and the p-channel transistors are moved closer together. “We believe that we can propose a roadmap for the next eight to 10 generations — with an introductory pace of two to two-and-a-half-year cadence,” he said.
Van den hoves’s roadmap sees forksheet devices as an extension of the standard nanosheet concept, “and we believe it will be introduced around the equivalent of the one nanometer generation,” he said. The Imec CEO also described a more complex GAA technology, where you are stacking nFET and pFET wires on top of each other, which is known as a complimentary FET (CFET) device.
According to Imec simulations, forksheet devices with reduced n-to-p spacing show a 10 percent performance increase compared to nanosheet devices and a 20 percent cell area reduction compared to GAA nanosheet devices. When implemented in an SRAM design, the simulations reveal a combined cell area scaling and performance increase of 30 percent for 8nm p-n spacing.
Again, according to Imec, electrical characterization results confirm that the forksheet is a promising device architecture to extend the logic and SRAM scaling roadmaps beyond 2nm while leveraging nanosheet integration in a non-disruptive way.
Continuing scaling beyond the forksheet device, the CFET architecture where n- and pMOS devices are vertically stacked on top of each other could overcome anticipated limitations with forksheet refinements. Stacking removes the n-p spacing from cell height considerations, allowing further maximization of the effective channel width and the drive current.
Because of its reduced n-to-p separation, the forksheet is expected to have superior area and performance scalability. Compared to a nanosheet device, researchers have reported a 10 percent speed gain (at constant power) and a 24 percent power reduction (at constant speed).
At its research lab in Belgium, Imec has shown working versions of a transistor structure that could be used for 2nm and 1nm chip designs. Imec puts the need for 2nm process technology emerging in 2023 for risk production with mass production by the end of 2024 or early 2025.
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