A new approach to IC design subdivides a system into functional circuit blocks called "chiplets,” referring to the independent constituents which make up a large chip built out of multiple smaller dies connected together on a multi-chip module (MCM).
For more than 50 years, the number of transistors that could be squeezed onto a piece of silicon increased in lockstep with Moore’s Law. But since 2016, it has become apparent that the scaling that let us witness a billion-fold increase in transistors on a chip over a matter of decades has been slowing. Designers have still been squeezing out more density, but it has come at a much higher cost of manufacturing devices on leading-edge process nodes – and it has taken much longer.
These developments have made the industry’s traditional method of building increasingly larger chips less appealing, both technically and economically. Engineers have had to consider an alternative path forward. Now, instead of designing sophisticated, monolithic chips that incorporate all the important elements on a single silicon die, major semiconductor companies are designing products that break those larger designs into smaller pieces, then combining them in new ways.
Process Flexibility
What makes chiplet design different from traditional SoC design methodologies is that many chiplet-based parts are assembled using pieces made with different process technologies. This makes sense as engineers have long recognized that not all of an SoC’s functionality requires the newest and most expensive process design. For example, a chiplet design might link a 7nm to 10nm CPU with a 14nm or 22nm I/O element over a high-speed internal interconnect.
What’s more, the growing diversity of integrated circuits (including CPUs, GPUs, FPGAs, and memory) means that it’s more desirable than ever to piece together larger ICs out of smaller dies, each purpose-built using the best process for the job.
It is common knowledge that some semiconductor components – for instance, analog signal processing and analog I/O – may be better off staying at larger process-manufacturing sizes. And since the smallest transistors are also the most difficult and most expensive to design and manufacture, systems made up of chiplets can reserve cutting-edge technology for the parts of the design where that investment is most cost-effective.
Smaller Dies, Higher Quality
In addition, smaller pieces of silicon are also inherently less prone to manufacturing defects, meaning that breaking down a large die into smaller chiplets improves yield.
Studies have shown that a 360 mm² monolithic die will have a yield of 15 percent, while a 4-chiplet design (with each chiplet measuring 99 mm²) more than doubles the yield to 37 percent. Chiplets are inherently cheaper to manufacture since they waste less wafer space (smaller chips result in less wasted wafer as a percentage of the total).
Chiplets communicate through high-speed, high-bandwidth connections. And because the bandwidth is high between these chips, they will function exactly as if they are a single chip.
New Advances from Major Chip Producers
Both Intel and AMD are pursuing the use of chiplets in their next-generation servers. AMD’s 3rd generation Ryzen CPUs, for example, are based on chiplet design principles that interconnect multiple CPU cores. As a result of efforts by these and other chipmakers, there have been some important advancements in chip packaging and interconnect technologies that are making the process of building chiplets more efficient.
For example, Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology provides horizontal, or 2D, connections across different chiplet elements. Intel’s solution to the problem of developing independent chiplets on their own optimal processes, then interconnecting them in a single package to match the functionality of a monolithic SoC, is called Foveros. Foveros is a 3D stacking technology that allows it to stack logic chips atop one another. Intel’s latest development combines the two approaches and is called Co-EMIB, enabling both 2D-horizontal and 3D-vertical connections of components in a single package.
TSMC, the world’s largest foundry, recently joined with Arm in announcing a new 7nm chiplet system operating at 4GHz. The system employs four Arm Cortex-A72 processors and TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) packaging.
The TSMC/Arm chiplet features a low-voltage-in-package-interconnect (LIPINCON) developed by TSMC that is said to reach data rates of 8Gbps per pin with power efficiency of 0.56 pico-Joules per bit (pJ/bit). The TSMC/Arm die-to-die inter-chiplet connection further features 1.6 terabits per second per square millimeter (Tbps/mm²) bandwidth density.
Going forward, the mix-and-match approach chiplets allow will be well-suited for applications such as AI acceleration, 5G communications and self-driving cars. Autonomous driving in particular will place significantly higher demands on integration technology: the data transfer rate between circuits must be very high because of the amount of camera image and radar or LiDAR data being processed, and therefore regularly exchanged between the circuits.
